The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for forming a gate pattern in a semiconductor device.
During a typical process for forming a gate pattern in a dynamic random access memory (DRAM), a critical dimension (CD) of a peripheral region is formed small to form a high speed device. However, it is difficult to exclusively decrease the CD of the peripheral region. Pattern densities in a cell region and the peripheral region are different from each other. The patterns in the peripheral region have various shapes. Thus, decreasing the CD smaller than a certain size is difficult.
Currently, various methods including optical proximity correction (OPC), lithography, and etch are used for decreasing the CD of the peripheral region.
However, there may be a limitation in decreasing the CD of the peripheral region when performing the OPC method using a scattering bar. The lithography method may cause a notching or a collapse when overly decreasing the CD. The etch method can decrease the CD by adjusting a bias. However, the OPC, the lithography, and the etch methods adjust the CD in both the cell region and the peripheral region at substantially the same time. Thus, it is difficult to decrease the CD of the peripheral region exclusively while uniformly maintaining the CD of the cell region.
Thus, a method for decreasing the CD of the peripheral region exclusively while uniformly maintaining the CD of the cell region may be required.